`timescale  1ns / 1ps
`include "code\source\P1\scrambler.v"

module tb_scrambler;

// scrambler Parameters
parameter PERIOD = 10;


// scrambler Inputs
reg clk = 0 ;
reg rst_n = 0 ;
reg [6: 0] seed = 0 ;
reg load = 0 ;
reg din = 0 ;
reg din_valid = 0 ;

// scrambler Outputs
wire dout ;
wire dout_valid ;


always begin
    #(PERIOD / 2) clk = ~clk;
end
       


initial begin
    $dumpfile("./release/test_scrambler.vcd");
    $dumpvars(0, tb_scrambler);
end

scrambler u_scrambler (
              .clk ( clk ),
              .rst_n ( rst_n ),
              .seed ( seed [6: 0] ),
              .load ( load ),
              .din ( din ),
              .din_valid ( din_valid ),

              .dout ( dout ),
              .dout_valid ( dout_valid )
          );

initial begin
    rst_n <= 0;
    seed <= 7'b1111111;
    #20
    rst_n <= 1;
    #10
    load <= 1;
    #10
    load <= 0;
    #5
    din_valid = 1;
    #1270
    din_valid = 0;
    #50
    $finish;
end

endmodule
